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डेटा पत्रक - Spartan-II 2.5V FPGA Family:Introduction and Ordering Information - Xilinx

भाग संख्या XC2S15-xxxx
समारोह Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
मैन्युफैक्चरर्स Xilinx 
लोगो Xilinx लोगो 
पूर्व दर्शन
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XC2S15-xxxx pdf
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information
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R
General Overview
The Spartan-II family of FPGAs have a regular, flexible, pro-
grammable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited reprogram-
ming cycles are possible with this approach. Stored values
in these cells determine logic functions and interconnec-
tions implemented in the FPGA. Configuration data can be
read from an external serial PROM (master serial mode), or
written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume applica-
tions where the versatility of a fast programmable solution
adds benefits. Spartan-II FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-II devices provide system clock
rates up to 200 MHz. Spartan-II FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-II
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
The Xilinx XC17S00A PROM family is recommended for
serial configuration of Spartan-II FPGAs. The In-System
Programmable (ISP) XC18V00 PROM family is recom-
mended for parallel or serial configuration.
DLL
CLBs
CLBs
DLL
CLBs
CLBs
DLL DLL
I/O LOGIC
XC2S15
Figure 1: Basic Spartan-II Family FPGA Block Diagram
DS001_01_091800
2
www.xilinx.com
DS001-1 (v2.3) November 1, 2001
1-800-255-7778
Preliminary Product Specification

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XC2S15-xxxxSpartan-II 2.5V FPGA Family:Introduction and Ordering InformationXilinx
Xilinx


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