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EDI2DL32256V डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 256Kx32 Synchronous Pipline Burst SRAM - White Electronic

भाग संख्या EDI2DL32256V
समारोह 256Kx32 Synchronous Pipline Burst SRAM
मैन्युफैक्चरर्स White Electronic 
लोगो White Electronic लोगो 
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EDI2DL32256V pdf
EDI2DL32256V
Pin
Various
L5,G5
G3,L3
M4
K4
E4
F4
B4
R3
T7
Various
Various
Various
Symbol
A0-17
BE0\,BE1\,
BE2\,BE3\
BWE\
CLK
CE\
OE\
ADSC\
MODE
ZZ
DQ0-31
Vcc
Vss
Type
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Input
Synchronous
Input
Input
Synchronous
Input/Output
Supply
Ground
PIN DESCRIPTIONS
Description
Addresses: These inputs are registered and must meet setup and hold times around the rising edge
of CLK.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls
DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31
Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
times around the rising edge of CLK.
Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on
its rising edge. All synchronous inputs must meet setup and hold times around the clockís rising edge.
Chip Enable: This active LOW inputs is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data output drivers
Address Status Controller: This active LOW input causes device to be deselected or selected along with new
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal
operation, this input has to be either LOW or NC (no connect)
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31
Core power supply: +3.3V -5%/+5%
Ground
TRUTH TABLE
Operation
Address Used
CE\
ADSC\
WRITE\
Deselected Cycle, Power Down
None
HL
X
WRITE Cycle, Begin Burst
External
LL
L
READ Cycle, Begin Burst
External
LL
H
READ Cycle, Begin Burst
External
LL
H
READ Cycle, Suspend Burst
Current
XH
H
READ Cycle, Suspend Burst
Current
XH
H
READ Cycle, Suspend Burst
Current
HH
H
READ Cycle, Suspend Burst
Current
HH
H
WRITE Cycle, Suspend Burst
Current
XH
L
WRITE Cycle, Suspend Burst
Current
HH
L
OE\ DQ
X High-Z
XD
LQ
H High-Z
LQ
H High-Z
LQ
H High-Z
XD
XD
NOTE:
1. X means ìdonít careî, H means logic HIGH. L means logic LOW.
2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW
2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH
3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle
5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though
out the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
November 2000, Rev. 1
ECO #13417

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भाग संख्याविवरणविनिर्माण
EDI2DL32256V256Kx32 Synchronous Pipline Burst SRAMWhite Electronic
White Electronic


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