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XC2C512 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Coolrunner-ii CPLD - Xilinx

भाग संख्या XC2C512
समारोह Coolrunner-ii CPLD
मैन्युफैक्चरर्स Xilinx 
लोगो Xilinx लोगो 
पूर्व दर्शन
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<?=XC2C512?> डेटा पत्रक पीडीएफ

XC2C512 pdf
XC2C512 CoolRunner-II CPLD
R
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Four I/O banks are available on the CoolRunner-II 512
macrocell device that permits easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 512 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 512 macrocell features LVCMOS,
LVTTL, SSTL, and HSTL I/O implementations. See Table 1
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a VREF pin
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C512(1)
IOSTANDARD Output
Attribute
VCCIO
LVTTL
3.3
Input
VCCIO
3.3
Input
VREF
N/A
LVCMOS33
3.3 3.3 N/A
LVCMOS25
2.5 2.5 N/A
LVCMOS18
1.8 1.8 N/A
LVCMOS15(2)
1.5
1.5 N/A
HSTL_1
1.5 1.5 0.75
SSTL2_1
2.5 2.5 1.25
SSTL3_1
3.3 3.3 1.5
(1) For information on Vref pins, see XAPP399.
(2) LVCMOS15 requires Schmitt-trigger inputs.
Board
Termination
Voltage VTT
N/A
N/A
N/A
N/A
N/A
0.75
1.25
1.5
250
200
150
100
50
0
0 20 40
60 80 100 120 140 160 180
Frequency (MHz)
Figure 1: ICC vs Frequency
DS096_01_030705
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 20 40 60 80 100 120
Typical ICC (mA)
0.025 17.22 34.37 52.04 69.44
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
86.85 105.13
140
122.68
160
140.23
180
157.78
2
www.xilinx.com
DS096 (v3.2) March 8, 2007
Product Specification

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