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74HC166 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 8-bit parallel-in/serial-out shift register - Philips

भाग संख्या 74HC166
समारोह 8-bit parallel-in/serial-out shift register
मैन्युफैक्चरर्स Philips 
लोगो Philips लोगो 
पूर्व दर्शन
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<?=74HC166?> डेटा पत्रक पीडीएफ

74HC166 pdf
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT166
FEATURES
Synchronous parallel-to-serial applications
Synchronous serial data input for easy expansion
Clock enable for “do nothing” mode
Asynchronous master reset
For asynchronous parallel data load see “165”
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q0
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0 Q1 Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay
CP to Q7
MR to Q7
maximum clock frequency
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC HCT
UNIT
15 20 ns
14 19 ns
63 50 MHz
3.5 3.5 pF
41 41 pF
December 1990
2

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