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74HC165 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 8-bit parallel-in/serial-out shift register - Philips

भाग संख्या 74HC165
समारोह 8-bit parallel-in/serial-out shift register
मैन्युफैक्चरर्स Philips 
लोगो Philips लोगो 
पूर्व दर्शन
1 Page
		
<?=74HC165?> डेटा पत्रक पीडीएफ

74HC165 pdf
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT165
FEATURES
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q7 and
Q7) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D0 to
D7 inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
Ds input and shifts one place to the right
(Q0 Q1 Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
tPHL/ tPLH
fmax
CI
CPD
propagation delay
CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
maximum clock frequency
input capacitance
power dissipation capacitance per
package
CONDITIONS
TYPICAL
HC HCT
CL = 15 pF; VCC = 5 V
16
15
11
14
17
11
56 48
3.5 3.5
notes 1 and 2
35
35
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
UNIT
ns
ns
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2

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