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TDA9103 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - DEFLECTION PROCESSOR FOR MULTISYNC MONITOR - ST Microelectronics

भाग संख्या TDA9103
समारोह DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
मैन्युफैक्चरर्स ST Microelectronics 
लोगो ST Microelectronics लोगो 
पूर्व दर्शन
1 Page
		
<?=TDA9103?> डेटा पत्रक पीडीएफ

TDA9103 pdf
TDA9103
PIN-OUT DESCRIPTION
Pin N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
PLL2C
H-DUTY
H-FLY
H-GND
H-REF
S4
S3
S2
S1
C0
R0
PLL1F
HLOCK-CAP
FH-MIN
H-POS
XRAY-IN
H-SYNC
VCC
GND
H-OUTEM
H-OUTCOL
B+ OUT
SBLK OUT
VGND
VAGCCAP
VREF
VCAP
VS-AMP
VS-CENT
VOUT
V-AMP
VDCOUT
V-POS
VSYNC
PLL1INHIB
E/WOUT
E/W- AMP
KEYST
B+ ADJ
REGIN
COMP
ISENSE
Function
Second PLL Loop Filter
DC Control of Horizontal Drive Output Pulse Duty-cycle.
If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a
capacitor on this pin a soft-start function may be realized on h-drive output.
Horizontal Flyback Input (positive Polarity)
Horizontal Section Ground. Must be connected only to components related to H blocks.
Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4
Hor S-CAP Switching
Hor S-CAP Switching
Hor S-CAP Switching
Hor S-CAP Switching
Horizontal Oscillator Capacitor. To be connected to Pin 4.
Horizontal Oscillator Resistor. To be connected to Pin 4.
First PLL Loop Filter. To be connected to Pin 4.
First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change
detected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the
duration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4.
DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage
generated by a resistor bridge connected between Pin 5 and 4.
DC Control for Horizontal Centering
X-RAY Protection Input (with internal latch function)
TTL Horizontal Sync Input
Supply Voltage (12V Typical)
Ground
Horizontal Drive Output (emiter of internal transistor). See description on pages 15-16.
Horizontal Drive Output (open collector of internal transistor). See description on pages 15-16.
B+ PWM Regulator Output
Safety Blanking Output. Activated during frequency changes, when X-RAY input is
triggered or when VS is too low.
Vertical Section Signal Ground
Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
Vertical Section Reference Voltage
Vertical Sawtooth Generator Capacitor
DC Control of Vertical S Shape Amplitude
DC Control of Vertical S Centering
Vertical Ramp Output (with frequency independant amplitude and S-correction)
DC Control of Vertical Amplitude Adjustment
Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output
DC Control of Vertical Position Adjustment
Vertical TTL Sync Input
TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal)
East/West Pincushion Correction Parabola Output
DC Control of East/West Pincushion Correction Amplitude
DC Control of Keystone Correction
DC Control of B+ Adjustment
Regulation Input of B+ Control Loop
B+ Error Amplifier Output for Frequency Compensation and Gain Setting
Sensing of External B+ Switching Transistor Emiter Current
2/27

विन्यास 27 पेज
डाउनलोड[ TDA9103 Datasheet.PDF ]


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