DataSheet.in

M2081 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN - Integrated Circuit Solution Inc

भाग संख्या M2081
समारोह VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
मैन्युफैक्चरर्स Integrated Circuit Solution Inc 
लोगो Integrated Circuit Solution Inc लोगो 
पूर्व दर्शन
1 Page
		
<?=M2081?> डेटा पत्रक पीडीएफ

M2081 pdf
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
5
8
6
7
11, 19, 33
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
Input
Output
Input
Power
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Power supply connection, connect to +3.3V.
Automatic/manual reselection mode for clock input:
12
AUTO
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
Reference Acknowledgement pin for input mux state; outputs
13
REF_ACK
Output
the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output No internal terminator Clock output pair. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor1
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 8,
P Divider Look-Up Table (LUT), on pg. 4.
20
21
nDIF_REF1
DIF_REF1
Input
Biased to Vcc/2 2
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Internal pull-down resistor 1 Resistor bias on inverting terminal supports TTL or LVCMOS.
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
Input clock frequency selection. LVCMOS/LVTTL. See
Tables 3 and 4 Mfin Divider Look-Up Tables (LUT) on pg. 3.
29
30
FEC_SEL0
FEC_SEL1
Input
Internal pull-down resistor1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
See Tables 5, 6, and 7 on pg. 3.
31 LOL Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
32 NBW Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 11.
Table 2: Pin Descriptions
Note 2: Biased toVcc/2, with 50kto Vcc and 50kto ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Note 3: See LVCMOS Outputs in DC Characteristics on pg. 11.
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
2 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

विन्यास 14 पेज
डाउनलोड[ M2081 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
M208Single Chip OrganSTMicroelectronics
STMicroelectronics
M208-A4Contact Image Sensor ModuleCMOS Sensor
CMOS Sensor


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English