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M2021 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - VCSO BASED CLOCK PLL - Integrated Circuit Systems

भाग संख्या M2021
समारोह VCSO BASED CLOCK PLL
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=M2021?> डेटा पत्रक पीडीएफ

M2021 pdf
Integrated
Circuit
Systems, Inc.
M2020/21
VCSO BASED CLOCK PLL
Product Data Sheet
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
5
8
6
7
11, 19, 33
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
Input
Output
Input
Power
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output No internal terminator Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Output No internal terminator Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor1
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT), on pg. 3.
20
21
nDIF_REF1
DIF_REF1
Input
Biased to Vcc/2 2
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Internal pull-down resistor 1 Resistor bias on inverting terminal supports TTL or LVCMOS.
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
Input clock frequency selection. LVCMOS/LVTTL.
See Table 3, Mfin Divider Look-Up Table (LUT) on pg. 3.
29
30
MR_SEL0
MR_SEL1
Input
Internal pull-down resistor1
M and R divider value selection. LVCMOS/ LVTTL.
See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.
31 LOL Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32
34, 35, 36
NBW
DNC
Narrow Bandwidth enable. LVCMOS/LVTTL:
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
Do Not Connect.
Internal nodes. Connection to these pins can cause erratic
device operation.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 8.
Table 2: Pin Descriptions
Note 2: Biased toVcc/2, with 50kto Vcc and 50kto ground. See Differential Inputs Biased to VCC/2 on pg. 8.
Note 3: See LVCMOS Output in DC Characteristics on pg. 8.
M2020/21 Datasheet Rev 1.0
2 of 10
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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