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954226 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Controller - Renesas

भाग संख्या 954226
समारोह Programmable Timing Controller
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
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<?=954226?> डेटा पत्रक पीडीएफ

954226 pdf
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
TSSOP Pin Description
PIN #
1 VDDPCI
2 GND
3 PCICLK3
4 PCICLK4
5 PCICLK5
6 GND
7 VDDPCI
PIN NAME
8 ITP_EN/PCICLK_F0
9 **SELPCIEX_LCDCLK#/PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 FSLA/USB_48MHz
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FSLB/TEST_MODE
17 LCDCLK_SS/PCIEX0T
18 LCDCLK_SS/PCIEX0C
19 PCIEXT1
20 PCIEXC1
21 VDDPCIEX
22 PCIEXT2
23 PCIEXC2
24 PCIEXT3
25 PCIEXC3
26 SATACLKT
27 SATACLKC
28 VDDPCIEX
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
2
0930A—04/13/10

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डाउनलोड[ 954226 Datasheet.PDF ]


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