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FR1502 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - FIFO Buffer Register - Western Digital

भाग संख्या FR1502
समारोह FIFO Buffer Register
मैन्युफैक्चरर्स Western Digital 
लोगो Western Digital लोगो 
पूर्व दर्शन
1 Page
		
<?=FR1502?> डेटा पत्रक पीडीएफ

FR1502 pdf
INTERFACE SIGNALS DESCRIPTIONS
PIN
NUMBER
SIGNAL NAME SYMBOL
FUNCTION
25-2B,
2-6
INPUT REGISTER
FR1502-00
-01
-02
FR1502-10
-11
-12
IRO-
IRB
IRO-
IRB
Input data lines. These are input (but not latched) to the FIFO
when the Input Enable and Input Strobe are active (high).
Input data lines. These are input (but not latched) to the FIFO in-
dependently of the Input Enable or Input Strobe.
20 INPUT REGISTER
EMPTY
FR1502-00
-01
-02
FR1502-10
-11
-12
IRE When high, indicates that data can be loaded into the FIFO. It is
reset to a low by falling edge of the Input Strobe.
IRE When high, indicates that data can be loaded into the FIFO. It is
reset to a low by a rising edge of the Input Strobe.
22 INPUT STROBE
FR1502-00
-01
-02
IS Latches input data in the FIFO on a falling edge.
FR1502-10
-11
-12
24 MASTER RESET
IS Latches input data in the FIFO on a rising edge.
MR When high, clears the FIFO control registers. This leaves the
OUTPUT REGISTER DATA (ORO-ORB) in an undefined state.
sets INPUT REGISTER EMPTY (IRE) to high and resets OUT-
PUT DATA READY (ODR) to low.
19-11 OUTPUT REGISTER
DATA
ORO-
ORB
Three state data outputs. When OE is low, the outputs are in the
high impedance state. When OE is high, these lines present the
previous latched data in a first-in/first-out manner.
10 OUTPUT DATA
READY
ODR
ODR is high when data is latched and available at the data output
lines. Is reset to low by the falling edge of OUTPUT STROBE
(OS) if OUTPUT ENABLE (OE) is high.
7 OUTPUT STROBE OS A falling edge of this signal resets the OUTPUT DATA READY
(ODR) line and then shifts the data one step towards the output
if OUTPUT ENABLE (OE) is high.
23 INPUT ENABLE
FR1502-00
-01
-02
FR1502-10
-11
-12
B OUTPUT ENABLE
1 Vss POWER
SUPPLY
IE
IE
OE
Vss
When high, enables the Input Register and Input Control logic.
When INPUT STROBE (IS) is high, the input data will be trans-
ferred into the FIFO. IS can then be used to latch the data.
When high, enables the Input Control Logic. At any state of IE or
IS, the input data will be transferred into the FIFO, but can not be
latched unless IE is high.
When low, OE puts the output lines (ORO-ORB) in high imped-
ance state. When high, the output lines present the output data.
+5VDC
21 Voo POWER
SUPPLY
Voo
OVolt-GND
9 VGG POWER
SUPPLY
VGG
-12VDC
56

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डाउनलोड[ FR1502 Datasheet.PDF ]


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