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HD74CDCF2510B डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3-V Phase-lock Loop Clock Driver - Renesas

भाग संख्या HD74CDCF2510B
समारोह 3.3-V Phase-lock Loop Clock Driver
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
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<?=HD74CDCF2510B?> डेटा पत्रक पीडीएफ

HD74CDCF2510B pdf
HD74CDCF2510B
Pin Arrangement
AGND 1
VCC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
VCC 10
G 11
FBOUT 12
(Top view)
24 CLK
23 AVCC
22 VCC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 VCC
13 FBIN
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
Input voltage *1
Output voltage *1, 2
VCC –0.5 to 4.6
VI –0.5 to 6.5
VO –0.5 to VCC +0.5
V
V
V
Input clamp current
IIK –50 mA VI < 0
Output clamp current
IOK ±50 mA VO < 0 or VO > VCC
Continuous output current
IO ±50 mA VO = 0 to VCC
Supply current
ICC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT 0.7 W
Storage temperature
Tstg –65 to +150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board
trace length of 750 mils.
Rev.10.00 Apr 07, 2006 page 2 of 7

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डाउनलोड[ HD74CDCF2510B Datasheet.PDF ]


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