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CY7C09359AV डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM - Cypress Semiconductor

भाग संख्या CY7C09359AV
समारोह 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM
मैन्युफैक्चरर्स Cypress Semiconductor 
लोगो Cypress Semiconductor लोगो 
पूर्व दर्शन
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<?=CY7C09359AV?> डेटा पत्रक पीडीएफ

CY7C09359AV pdf
CY7C09349AV
CY7C09359AV
Functional Description
The CY7C09349AV and CY7C09359AV are high-speed 3.3 V
synchronous CMOS 4 K and 8 K × 18 dual-port static RAMs. Two
ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.[2]
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
tCD2 = 9 ns (pipelined). Flow-through mode can also be used to
bypass the pipelined output register to eliminate access latency.
In flow-through mode data will be available tCD1 = 20 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple chip enables allows easier
banking of multiple chips for depth expansion configurations. In
the pipelined mode, one cycle is required with CE0 LOW and CE1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s address strobe
(ADS). When the port’s count enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin thin quad plastic flatpack
(TQFP) packages.
Note
2. When simultaneously writing to the same location, final value cannot be guaranteed.
Document Number: 001-63888 Rev. *C
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भाग संख्याविवरणविनिर्माण
CY7C09359AV3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAMCypress Semiconductor
Cypress Semiconductor


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