CYWB0125AB डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - West Bridge Antioch - Cypress Semiconductor

भाग संख्या CYWB0125AB
समारोह West Bridge Antioch
मैन्युफैक्चरर्स Cypress Semiconductor 
लोगो Cypress Semiconductor लोगो 
पूर्व दर्शन
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<?=CYWB0125AB?> डेटा पत्रक पीडीएफ

CYWB0125AB pdf
CYWB012X Family
West Bridge® Antioch™ is a peripheral mass storage controller
that enhances a processor system with flexible mass storage
support and high speed USB connectivity.
Antioch has three different ports that enable connections among
a main processor (P-Port), one or more mass storage devices
(S-Port), and a USB host (U-Port). Antioch’s unique SLIM
architecture allows these three ports to interact simultaneously
and independently of each other. This offers connectivity from
USB to Storage (typically used for PC high speed data
download), from USB to Processor (used for synchronization
operations), and from Processor to Storage.
Connected as a slave to a main processor, Antioch adds support
for high speed USB and mass storage access including MMC,
MMC+, SDIO, CE-ATA, SLC and MLC NAND. Antioch further
enables new usage models by allowing USB to directly connect
to a storage device independent of the main processor.
Antioch is primarily targeted at handsets, to enable high speed
connectivity to a PC through USB, and support for the latest
mass storage devices.
Antioch can, for instance, enable a multimedia phone to support
HDD or NAND MLC storage, with the ability to download
multimedia data at high speed from a PC directly to the storage
SLIM Architecture
The Simultaneous Link to Independent Multimedia (SLIM)
architecture allows three interfaces (P-port, S-port, and U-port)
to connect to one another independent of each other.
With this architecture, connecting the device using Antioch to a
PC through USB does not disturb any of the functions of the
device, which can still access mass storage, at the same time
the PC is synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
PC can access a mass storage device independent of the main
processor, or enumerate access to both the mass storage and
the main processor at the same time.
In a handset, this enables to use the phone as a thumb drive or
download media files to the phone while still having full
functionality available on the phone. It also allows using the
same phone as a modem to connect the PC to the web.
Mass Storage Support (S-Port)
The S-Port can be configured in two different modes, either
simultaneously supporting an SDIO/MMC+/CE-ATA port and a
× 8 NAND port, or supporting a unique × 16 NAND access port.
Antioch, as part of its mass storage management functions, can
fully manage a NAND device. An embedded 8051 manages the
actual reading and writing of the NAND, along with its required
protocols, including Single Level Cell (SLC) and Multi-Level Cell
(MLC) NAND. It performs standard NAND management
functions such as ECC and wear leveling.
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface supports both
synchronous and asynchronous SRAM-mapped memory
accesses. This ensures straightforward electrical
communications with the processor, which may also have other
devices connected on a shared memory bus.
The memory address is decoded to access any of the multiple
endpoint buffers inside Antioch. These endpoints serve as
buffers for data between each pair of ports, for example, between
the processor port and the USB port. The processor writes and
reads into these buffers via the memory interface.
Access to these buffers is controlled by either using a DMA
protocol or an interrupt to the main processor. These two modes
are configurable by the external processor.
As a DMA slave, Antioch generates a DMA request signal to
signify to the main processor that a specific buffer is ready to be
read from or written to. The external processor monitors this
signal and polls Antioch for the specific buffers ready for read or
write. It then performs the appropriate read or write operations
on the buffer through the processor interface. This way, the
external processor only deals with the buffers to access a
multitude of storage devices connected to Antioch.
In the Interrupt mode, Antioch communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Antioch for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations via the processor interface.
The West Bridge Antioch device includes configuration and
status registers that are accessible as memory-mapped
registers through the processor interface. The configuration
registers allow the system to specify certain behavior of Antioch.
For example, it can mask certain status registers from raising an
interrupt. The status registers convey various status of Antioch,
such as the addresses of buffers for read operations.
The West Bridge Antioch is available in two packaging options:
As a bare die or in a 6 × 6 mm, 100-pin very fine-pitch ball grid
array (VFBGA). As a 100-pin VFBGA, it consumes a small
amount of space and allows for easy debug and connections to
the other devices in the system.
Document #: 001-05898 Rev.*C
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भाग संख्याविवरणविनिर्माण
CYWB0125ABWest Bridge AntiochCypress Semiconductor
Cypress Semiconductor

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