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MCM62940A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 32K x 9 Bit BurstRAM Synchronous Static RAM - Motorola

भाग संख्या MCM62940A
समारोह 32K x 9 Bit BurstRAM Synchronous Static RAM
मैन्युफैक्चरर्स Motorola 
लोगो Motorola लोगो 
पूर्व दर्शन
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<?=MCM62940A?> डेटा पत्रक पीडीएफ

MCM62940A pdf
BLOCK DIAGRAM (See Note)
BAA-----------------------------a
K----------~--------------._--,
BURST LOGIC
BINARY
COUNTER
INTERNAL
Ql
I
Al'
- -_
ADDRESS
_-,-~--~
15
r-~--~------.------iLOAD
01
ao AO'
DO
EXTERNAL
ADDRESS
A14-AO -+---------,~
ADDRESS
REGISTERS
Al AO
Al4-A2
15
32Kx9
MEMORY
ARRAY
I W-----a
WRITE
REGISTER
DATA·IN
REGISTERS
SO------------~
51-------------0
ENABLE
REGISTER
OUTPUT
BUFFER
G----------------------------------~
~oa8~--___,~--------------------------------------------------------~~------~
NOTE: All registers are positive-edge triggered. The TSC orTSP signals control the duration ofthe burst and the start ofthe next burst.When TSP
is sampled low, any ongoing burst is interrupted and a read (independent of Wand TSC) is performed using the new external address.
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed
using the next extemal address. Chip selects (SO, Sl) are sampled only when a new base address is loaded. After the first cycle of the
burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When
BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion
of a burst, the address will wrap around to its initial state. See BURST SEQUENCE GRAPH.
BURST SEQUENCE GRAPH (See Note)
rO'O~
~'.OJ'A1', AO'=
NOTE: The external two values for Aland AO .
provide the starting point for the burst
sequence graph. The burst logic ad-
vances Aland AO as shown above.
MCM62940A
4-86
MOTOROLA FAST SRAM DATA

विन्यास 8 पेज
डाउनलोड[ MCM62940A Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

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