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UT01VS50L डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Voltage Supervisor - Aeroflex Circuit Technology

भाग संख्या UT01VS50L
समारोह Voltage Supervisor
मैन्युफैक्चरर्स Aeroflex Circuit Technology 
लोगो Aeroflex Circuit Technology लोगो 
पूर्व दर्शन
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<?=UT01VS50L?> डेटा पत्रक पीडीएफ

UT01VS50L pdf
PIN DESCRIPTIONS
Number
1
Pins
MR
2 VDD
3 GND
4 PFI
5 PFO
6 WDI
7 RESET
Type
Digital Input
TTL/CMOS
compatible
Supply
Supply
Analog Input
Digital Output
Digital Input
Digital Output
Description
Manual Reset Input with an internal pull-up. Active low. MR low forces the reset
output RESET low. Required minimum MR pulse width is 150ns. RESET is held low
for duration of the reset timer.
Power supply. Operating voltage range is 4.75V to 5.5V. VDD level is monitored
internally by a dedicated comparator circuit, which employs an internal bandgap
voltage reference nominally equal to 1.25V. Every time VDD falls below the threshold
voltage, nominally 4.65V, RESET and WDO outputs are forced low. (See WDO and
RESET descriptions.) (Figure 4.)
ASIC Ground. This pin should be tied to ground and establishes the reference for
voltage detection.
Threshold detector input. Voltage on this input is fed directly to an internal
comparator where it is compared to the bandgap voltage reference of 1.25V. It can be
used for detection of low battery or power failure of voltage supplies other than VDD.
When voltage at PFI input drops below its threshold value of 1.25V, PFO output is
forced low, otherwise, stays high.
Threshold detector output. Active low, push-pull output driver. It responds directly
to PFI input. If PFI voltage is below the bandgap reference voltage, PFO is low. If PFI
is above the reference voltage, PFO output is high.
Watchdog timer input pin. This pin is typically used to monitor microprocessor
activity. It can assume three states: low, high and float. If WDI is floating or connected
to a high impedance three state buffer, the watchdog timer is not active, and the
corresponding watchdog output WDO is high. Watchdog timer is also not active any
time RESET is low. Providing that RESET is not asserted, any change of state at WDI
that is longer than 50ns will start the timer, or restart it, if the timer is already running
(Figure 3.). If there is no activity within the timeout period, nominally 1.6sec, the
timer will stop running and WDO output will go low (Figure 3).
Reset output. Active low, push-pull output driver. This output responds to both: VDD
monitoring circuits and the manual reset input MR.
On power up, RESET is guaranteed to be logic low for all VDD values from 1.2V up
to the reset threshold, nominally 4.65V. Once this threshold is reached, an internal
RESET timer is activated. During the countdown RESET output is kept low. It is
raised high upon completion of countdown, typically after 200ms. If a brown out
condition occurs during the reset timer countdown, the reset timer would be reset and
another countdown would start after VDD levels were restored above the reset
threshold. On power down, when VDD falls below the threshold voltage, RESET goes
low and is guaranteed to stay low until VDD drops below 1.2V.
If MR is asserted low, RESET is forced low and the reset timer is kept reset. When
MR is released high, the timer is activated and RESET is kept low until completion
of the reset timeout, when it is raised high.
2

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