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NB3H63143G डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Clock Generator - ON Semiconductor

भाग संख्या NB3H63143G
समारोह Programmable Clock Generator
मैन्युफैक्चरर्स ON Semiconductor 
लोगो ON Semiconductor लोगो 
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NB3H63143G pdf
NB3H63143G
BLOCK DIAGRAM
VDD PD# SEL0 SEL1
Reference XIN/ CLKIN
Clock
Crystal
XOUT
Input
Decoder
Crystal/Clock Control
Clock Buffer/
Crystal
Oscillator And
AGC
PLL Block
Phase
Detector
Configuration
Memory
Frequency
and SS
Output control
Output
Divider
Charge
Pump
Feedback
Divider
VCO
Output
Divider
PLL Bypass Mode
Output
Divider
CMOS/
DIFF
buffer
CMOS/
DIFF
buffer
CMOS
buffer
VDDO0
CLK0
OE0
VDDO1
CLK1
OE1
VDDO2
CLK2
OE2
GND GNDO
Notes:
1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. OE[2:0], SEL[1:0] have internal pull up resistors. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
XIN/CLKIN 1
16 15 14 13
NB3H63143G
12 VDD
XOUT 2
PD# 3
GNDO
(EPAD)
11 VDDO1
10 CLK1
GND 4
9 CLK0
5 67 8
Figure 2. Pin Connections (Top View) − QFN16 (with EPAD)
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NB3H63143GProgrammable Clock GeneratorON Semiconductor
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