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XC2C64A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CoolRunner-II CPLD - Xilinx

भाग संख्या XC2C64A
समारोह CoolRunner-II CPLD
मैन्युफैक्चरर्स Xilinx 
लोगो Xilinx लोगो 
पूर्व दर्शन
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XC2C64A pdf
XC2C64A CoolRunner-II CPLD
R
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See Table 1 for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64A
IOSTANDARD Output
Attribute
VCCIO
LVTTL
3.3
Input
VCCIO
3.3
Input
VREF
N/A
Board
Termination
Voltage VT
N/A
LVCMOS33
3.3 3.3 N/A
N/A
LVCMOS25
2.5 2.5 N/A
N/A
LVCMOS18
1.8 1.8 N/A
N/A
LVCMOS15(1) 1.5
1.5 N/A
1. LVCMOS15 requires Schmitt-trigger inputs.
N/A
20
15
10
5
0
0 50 100 150 200 250
Frequency (MHz)
Figure 1: ICC vs Frequency
DS092_01_092302
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 25 50 75 100 150 175
Typical ICC (mA)
0.017 1.8 3.7 5.5 7.48
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
11.0
12.7
200
14.6
225 240
15.3 17.77
2
www.xilinx.com
DS311 (v2.3) November 19, 2008
Product Specification

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डाउनलोड[ XC2C64A Datasheet.PDF ]


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