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XC2C32A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CoolRunner-II CPLD - Xilinx

भाग संख्या XC2C32A
समारोह CoolRunner-II CPLD
मैन्युफैक्चरर्स Xilinx 
लोगो Xilinx लोगो 
पूर्व दर्शन
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<?=XC2C32A?> डेटा पत्रक पीडीएफ

XC2C32A pdf
XC2C32A CoolRunner-II CPLD
R
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II CPLD 32 macrocell features both
LVCMOS and LVTTL I/O implementations. See Table 1 for
I/O standard voltages. The LVTTL I/O standard is a general
purpose EIA/JEDEC standard for 3.3V applications that use
an LVTTL input buffer and Push-Pull output buffer. The
20
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C32A
IOSTANDARD Output
Attribute
VCCIO
LVTTL
3.3
Input
VCCIO
3.3
Input
VREF
N/A
Board
Termination
Voltage VT
N/A
LVCMOS33
3.3 3.3 N/A
N/A
LVCMOS25
2.5 2.5 N/A
N/A
LVCMOS18
1.8 1.8 N/A
N/A
LVCMOS15(1) 1.5
1.5 N/A
1. LVCMOS15 requires Schmitt-trigger inputs.
N/A
15
10
5
0
0 50 100 150 200 250 300
Frequency (MHz)
Figure 1: ICC vs. Frequency
DS091_01_030105
Table 2: ICC vs. Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 25 50 75 100 150 175
Typical ICC (mA)
0.016 0.87 1.75 2.61 3.44 5.16
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
5.99
200
6.81
225
7.63
250
8.36
300
9.93
2
www.xilinx.com
DS310 (v2.1) November 6, 2008
Product Specification

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