VSC7105 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - 1.0625 Gbit/sec Transmitter/Receiver Chipset - Vitesse Semiconductor

भाग संख्या VSC7105
समारोह 1.0625 Gbit/sec Transmitter/Receiver Chipset
मैन्युफैक्चरर्स Vitesse Semiconductor 
लोगो Vitesse Semiconductor लोगो 
पूर्व दर्शन
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<?=VSC7105?> डेटा पत्रक पीडीएफ

VSC7105 pdf
1.0625 Gbit/sec Transmitter/Receiver Chipset
for Fibre Channel or Proprietary Serial Links
Data Sheet
VSC7105 Transmitter Functional Description
The VSC7105 is an ANSI X3T11 compatible Fibre Channel (FC) transmitter designed to work at the FC
baud rate of 1.0625 Gb/s. The VSC7105 performs the serialization of parallel data and simplifies system design
by performing clock multiplication from the parallel data clock. The VSC7105 has two modes of operation: 10-
bit and 20-bit. The functional block diagrams for the 20-bit and 10-bit modes are shown in Figure 1 and
Figure 2 respectively.
The VSC7105 accepts 8B/10B encoded TTL input data as one or two parallel 10 bit characters which are
clocked into the device at 1/10 or 1/20 of the baud rate. User data should be encoded for transmission using the
8B/10B block code described in the Fibre Channel specification or any other equivalent coding scheme with a
transition density of 40% or greater and a maximum run length of 6 consecutive 1’s or 0’s. The VSC7105 serial-
izes the input data and transmits it at a baud rate of 10 times the frequency of the REFCLK input. The device
includes a phase locked loop-based clock multiplier that generates the baud clock. This PLL is fully monolithic,
and requires no external components.
The parallel input port timing is derived from the REFCLK input. REFCLK is internally divided by two,
and driven off chip as complementary TTL outputs: TCLK and TCLKN. In 20-bit mode, the VSC7105 loads
parallel data on the falling edge of TCLK. TCLK thus provides a convenient means to clock the data source. For
10 bit mode, the VSC7105 loads parallel data on the rising edge of REFCLK. The rising edge of REFCLK cor-
responds to the falling edges of both TCLK and TCLKN. The system designer may either use the rising edge of
REFCLK or the falling edges of TCLK and TCLKN to clock the data source. Only data on T10:19 are used in
10-bit mode. The width of the input data bus is controlled by the DWS (Data Width Select) input. A logic LOW
on this input places the VSC7105 in 20-bit mode and a logic HIGH places the VSC7105 in 10-bit mode.
Output Enable controls are provided for each of the serial output ports. OE0 controls the primary outputs,
TX, while OE1 controls the secondary outputs, TLX. When an OE control is brought HIGH, the respective out-
put is forced to a logical HIGH state. For example, a logical HIGH on the TX differential outputs will cause TX-
to be LOW and TX+ to be HIGH. The secondary outputs can be used as a local loopback for system testing.
A three-level TEST signal is provided to facilitate functional testing and to select NRZ or NRZI data for-
mat. When TEST is left floating, REFCLK replaces the PLL-generated internal clock. For normal operation
using the PLL-generated bit clock in Fibre Channel compliant mode which uses NRZ formatting, the TEST pin
is tied to GND. For normal operation using NRZI formatting, the TEST pin is tied VDD.
Page 2
® VITESSE Semiconductor Corporation
G52079-0 Rev. 2.7

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